LAN91C111INS

Non-PCI Ethernet single chip, 10/100 Mbps, 128TQFP, 3.3V, 25 MHz, LAN91C111INS

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Price:: US $6.00~7.00 / piece [Get Latest Price]

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	US $6.00~7.00

PartNumber:: LAN91C111INS

Brand:: SMSC Corporation - SMSC | Pack: DIP | D/C: 10+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2012-04-24

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Part Number:LAN91C111INS
US $6.00 - 7.00
EKXG401ELL6R8MJ16S

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A50L-0001-0175

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Product Summary

The LAN91C111INS is a 10/100 Non-PCI Ethernet single chip designed to facilitate the implementation of a third generation of Fast Ethernet connectivity solutions for embedded applications. For this third generation of products, flexibility and integration dominate the design requirements. The LAN91C111INS is a mixed signal Analog/Digital device that implements the MAC and PHY portion of the CSMA/CD protocol at 10 and 100 Mbps. The design of LAN91C111INS will also minimize data throughput constraints utilizing a 32-bit, 16-bit or 8-bit bus Host interface in embedded applications.

Parametrics

LAN91C111INS absolute maximum ratings: (1)Operating Temperature Range: 0℃ to +85℃; (2)Storage Temperature Range: -55 to + 150℃; (3)Lead Temperature Range (soldering, 10 seconds): +325℃; (4)Positive Voltage on any pin, with respect to Ground: VCC + 0.3V; (5)Negative Voltage on any pin, with respect to Ground: -0.3V; (6)Maximum VCC: +5V.

Features

LAN91C111INS features: (1)Single Chip Ethernet Controller; (2)Dual Speed - 10/100 Mbps; (3)Fully Supports Full Duplex Switched Ethernet; (4)Supports Burst Data Transfer; (5)8 Kbytes Internal Memory for Receive and Transmit FIFO Buffers; (6)Enhanced Power Management Features; (7)Optional Configuration via Serial EEPROM Interface; (8)Supports 8, 16 and 32 Bit CPU Accesses; (9)Internal 32 Bit Wide Data Path (Into Packet Buffer Memory); (10)Early TX, Early RX Functions; (11)Built-in Transparent Arbitration for Slave Sequential; (12)Access Architecture; (13)Flat MMU Architecture with Symmetric Transmit and Receive Structures and Queues; (14)3.3V Operation with 5V Tolerant IO Buffers (See Pin List Description for Additional Details); (15)Single 25 MHz Reference Clock for Both PHY and; (16)MAC; (17)External 25Mhz-output pin for an external PHY; (18)supporting PHYs physical media.