(Hong Kong)
Product Summary
The GAL6002B20LP is a High Performance E2CMOS FPLA Generic Array Logic. Having an FPLA architecture, the GAL6002B20LP provides superior flexibility in state-machine design. The GAL6002B20LP offers the highest degree of functional integration, flexibility, and speed currently available in a 24-pin, 300-mil package. E2CMOS technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently.The GAL6002B20LP has 10 programmable Output Logic Macrocells (OLMC) and 8 programmable Buried Logic Macrocell (BLMC). In addition, there are 10 Input Logic Macrocells (ILMC) and 10 I/O Logic Macrocells (IOLMC). Two clock inputs are provided for independent control of the input and output macrocells.
Parametrics
GAL6002B20LP absolute maximum ratings: (1)Supply voltage VCC: –0.5 to +7V; (2)Input voltage applied: –2.5 to VCC +1.0V; (3)Off-state output voltage applied: –2.5 to VCC +1.0V; (4)Storage Temperature: –65 to 150℃; (5)Ambient Temperature with Power Applied: –55 to 125℃.
Features
GAL6002B20LP features: (1)HIGH PERFORMANCE ECMOS TECHNOLOGY: 15ns Maximum Propagation Delay; 75MHz Maximum Frequency; (2)ACTIVE PULL-UPS ON ALL PINS; (3)LOW POWER CMOS: 90mA Typical Icc; (4)UNPRECEDENTED FUNCTIONAL DENSITY: 78 x 64 x 36 FPLA Architecture; 10 Output Logic Macrocells.
Diagrams
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 GAL6001B-30LP |
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SPLD - Simple Programmable Logic Devices Use GAL22V10D |
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Negotiable |
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GAL6002B-15LP |
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SPLD - Simple Programmable Logic Devices HI PERF E2CMOS FPLA |
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Negotiable |
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GAL6002B-20LJ |
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SPLD - Simple Programmable Logic Devices Use GAL22V10D |
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GAL6002B-20LP |
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SPLD - Simple Programmable Logic Devices Use GAL22V10D |
Data Sheet |
Negotiable |
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GAL6002B-15LJ |
Lattice |
SPLD - Simple Programmable Logic Devices Use GAL22V10D |
Data Sheet |
Negotiable |
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GAL6001B-30LJ |
Lattice |
SPLD - Simple Programmable Logic Devices Use GAL22V10D |
Data Sheet |
Negotiable |
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