MC68360CEM25L

32-bit controller, 240-BFQFP, 5V, MC68360CEM25L, Freescale

Rated 5 Rating 5 | reviews | Write a review

Price:: US $4.00~6.00 / piece [Get Latest Price]

Reference price:

Qty (lots)	Price/lot
	US $4.00~6.00

PartNumber:: MC68360CEM25L

Brand:: Freescale Semiconductor, Inc - Freescale | Pack: DIP | D/C: 05+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

Place Order via Escrow Service

Sold By

Ms. Susan's store

(Hong Kong)

add to my favourite

100% Positive feedback

Detailed seller ratings

Visit Store

Contact Now

Esrcow Service

Place orders confidently and securely via it

Safe payments
Quick and easy transactions
Free service charges

Learn More >>

Previous Next

Products Upload time: 2012-05-14

From Other Seller

Part Number:MC68360CEM25L
US $4.00 - 6.00
A50L-0001-0175

US $100.00 - 100.00 / Piece
(0) Remove
FM31256-G

US $2.40 - 4.20 / Piece
(0) Remove
Quantity:

piece

Product Summary

The MC68360CEM25L is a 32-bit controller. The MC68360CEM25L IMB provides a common interface for all modules of the M68300 family, which allows Freescale to develop new devices more quickly by using the library of existing modules. Although the IMB definition always included an option for an on-chip 32-bit bus, the QUICC is the first device to implement this option. The MC68360CEM25L UICC is comprised of three modules: the CPU32+ core, the SIM60, and the CPM. The MC68360CEM25L utilizes the 32-bit IMB. The device offers automatic byte alignment features that are not offered on the CPU32. These features allow 16 or 32-bit data to be read or written at an odd address. The MC68360CEM25L automatically performs the number of bus cycles required.

Parametrics

MC68360CEM25L absolute maximum ratings: (1)Speed: 25MHz; (2)Voltage: 5V; (3)Package / Case: 240-BFQFP; (4)Packaging: Tray; (5)Lead Free Status: Contains Lead; (6)RoHS Status: RoHS Non-Compliant.

Features

MC68360CEM25L features: (1)32-Bit Version of the CPU32 Core (Fully Compatible with the CPU32); (2)Background Debug Mode; (3)Byte-Misaligned Addressing; (4)Up to 32 Address Lines (At Least 28 Always Available); (5)Complete Static Design (0-5-MHz Operation); (6)Slave Mode To Disable CPU32+ (Allows Use with External Processors); (7)Multiple QUICCs Can Share One System Bus (One Master); (8)Bus Monitor; (9)Double Bus Fault Monitor; (10)Spurious Interrupt Monitor; (11)Software Watchdog; (12)Periodic Interrupt Timer; (13)Low Power Stop Mode; (14)Clock Synthesizer; (15)Breakpoint Logic Provides On-Chip Hardware Breakpoints; (16)External Masters May Use On-Chip Features Such As Chip Selects; (17)On-Chip Bus Arbitration with No Overhead for Internal Masters.